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==Overview== Altos Design Automation, Inc. is an electronic design automation software company. Altos develops and markets cell and semiconductor intellectual property (IP) characterization tools that create library views for timing, signal integrity and power analysis and optimization.〔("Statistical timing gets modeling boost" ), ''EE Times'', 2007-01-15.〕〔("Characterization tool aids SSTA-library creation" ), ''EDN'', 2007-01-15.〕 The Altos tools are fully automated and the company claims that its tools are extremely fast. The Altos tools are used by engineers employing both corner-based and statistical-based design implementation flows to reduce time-to -market and improve yield.〔("Statistical timing revs for 45-nm era" ), ''EE Times'', 2006-07-03.〕〔("Altos Targets Statistical Timing Models" ), ''Electronic News'', 2006-07-03.〕 Altos is privately held and was founded in January 2005 in Santa Clara, California by former employees of Cadence Design Systems. All members of the team worked at CadMOS where they were responsible for the development of Signal Integrity analysis tools for both cell- and transistor-level digital IC designers. Its corporate headquarters is in San Jose, California. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Altos Design Automation」の詳細全文を読む スポンサード リンク
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